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for pricing, delivery, and ordering information, please contact maxim/dallas direct! at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. general description the max1291/max1293 low-power, 12-bit analog-to-dig-ital converters (adcs) feature a successive-approxima- tion adc, automatic power-down, fast wake-up (2?), an on-chip clock, +2.5v internal reference, and a high- speed, byte-wide parallel interface. they operate with a single +3v analog supply and feature a v logic pin that allows them to interface directly with a +1.8v to +5.5vdigital supply. power consumption is only 5.7mw (v dd = v logic ) at the maximum sampling rate of 250ksps. two software-selec-table power-down modes enable the max1291/ max1293 to be shut down between conversions; accessing the parallel interface returns them to normal operation. powering down between conversions can cut supply current to under 10? at reduced sampling rates. both devices offer software-configurable analog inputs for unipolar/bipolar and single-ended/pseudo-differen- tial operation. in single-ended mode, the max1291 has eight input channels and the max1293 has four input channels (four and two input channels, respectively, when in pseudo-differential mode). excellent dynamic performance and low power, com- bined with ease of use and small package size, make these converters ideal for battery-powered and data- acquisition applications or for other circuits with demand- ing power consumption and space requirements. the max1291/max1293 tri-states int when cs goes high. refer to max1261/max1263 if tri-stating int is not desired. the max1291 is available in a 28-pin qsop package, while the max1293 is available in a 24-pin qsop. forpin-compatible +5v, 12-bit versions, refer to the max1290/max1292 data sheet. applications industrial control systems data logging energy management patient monitoring data-acquisition systems touch screens features ? 12-bit resolution, 0.5 lsb linearity ? +3v single operation ? user-adjustable logic level (+1.8v to +3.6v) ? internal +2.5v reference ? software-configurable, analog input multiplexer 8-channel single-ended/4-channel pseudo-differential (max1291) 4-channel single-ended/ 2-channel pseudo-differential (max1293) ? software-configurable, unipolar/bipolar inputs ? low power: 1.9ma (250ksps) 1.0ma (100ksps)400a (10ksps) 2a (shutdown) ? internal 3mhz full-power bandwidth track/hold ? byte-wide parallel (8 + 4) interface ? small footprint: 28-pin qsop (max1291) 24-pin qsop (max1293) max1291/max1293 250ksps, +3v, 8-/4-channel, 12-bit adcs with +2.5v reference and parallel interface ________________________________________________________________ maxim integrated products 1 19-1532; rev 3; 12/02 part max1291 acei 0? to +70? temp range pin-package 28 qsop ordering information pin configurations ?.5 inl (lsb) max1291bcei 0? to +70? ? 28 qsop ordering information continued at end of data sheet. typical operating circuits appear at end of data sheet. 15 14 ch7 cs qsop top view 2827 26 25 24 23 22 21 20 19 18 17 16 12 3 4 5 6 7 8 9 1011 12 13 v logic v dd refrefadj gnd com ch0 ch1 ch2 ch3 ch4 ch5 ch6 clk wr rd int d0/d8 d1/d9 d2/d10 d3/d11 d4 d5 d6 d7 hben max1291 pin configurations continued at end of data sheet. evaluation kit available max1291beei max1291aeei -40? to +85? ? -40? to +85? ?.5 28 qsop 28 qsop downloaded from: http:///
max1291/max1293 250ksps, +3v, 8-/4-channel, 12-bit adcs with +2.5v reference and parallel interface 2 _______________________________________________________________________________________ absolute maximum ratings electrical characteristics(v dd = v logic = +2.7v to +3.6v, com = gnd, refadj = v dd , v ref = +2.5v, 4.7? capacitor at ref pin, f clk = 4.8mhz (50% duty cycle); t a = t min to t max , unless otherwise noted. typical values are at t a = +25?.) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. v dd to gnd ..............................................................-0.3v to +6v v logic to gnd.........................................................-0.3v to +6v ch0?h7, com to gnd ............................-0.3v to (v dd + 0.3v) ref, refadj to gnd ................................-0.3v to (v dd + 0.3v) digital inputs to gnd ...............................................-0.3v to +6v digital outputs (d0?11, int ) to gnd...-0.3v to (v logic + 0.3v) continuous power dissipation (t a = +70?) 24-pin qsop (derate 9.5mw/? above +70?) ...........762mw 28-pin qsop (derate 8.00mw/? above +70?) .........667mw operating temperature ranges max1291_c_ _/max1293_c_ _ ..............................0? to +70? max1291_e_ _/max1293_e_ _ ...........................-40? to +85? storage temperature range .............................-65? to +150? lead temperature (soldering, 10s) .................................+300? external acquisition or external clock mode internal acquisition/internal clock mode max129_a external acquisition/internal clock mode external clock mode -3db rolloff sinad > 68db f in = 125khz, v in = 2.5v p-p (note 4) f in1 = 49khz, f in 2 = 52khz max129_b no missing codes over temperature conditions ns 50 aperture delay ns 625 t acq track/hold acquisition time ? 3.2 3.6 4.1 2.5 3.0 3.5 3.3 t conv conversion time (note 5) mhz 3 full-power bandwidth khz 250 full-linear bandwidth db -78 channel-to-channel crosstalk db 76 imd intermodulation distortion db 80 sfdr spurious-free dynamic range db -78 total harmonic distortion(including 5th-order harmonic) thd ?.5 inl relative accuracy (note 2) bits 12 res resolution db 67 70 sinad signal-to-noise plus distortion lsb ?.2 channel-to-channel offsetmatching ppm/? ?.0 gain temperature coefficient lsb ? lsb ? dnl differential nonlinearity lsb ? offset error lsb ? gain error (note 3) units min typ max symbol parameter internal acquisition/internal clock mode external acquisition or external clock mode <200 ps <50 aperture jitter mhz 0.1 4.8 f clk external clock frequency % 30 70 duty cycle dc accuracy (note 1) dynamic specifications (f in(sine wave) = 50khz, v in = 2.5v p-p , 250ksps, external f clk = 4.8mhz, bipolar input mode) conversion rate downloaded from: http:///
max1291/max1293 250ksps, +3v, 8-/4-channel, 12-bit adcs with +2.5v reference and parallel interface _______________________________________________________________________________________ 3 electrical characteristics (continued)(v dd = v logic = +2.7v to +3.6v, com = gnd, refadj = v dd , v ref = +2.5v, 4.7? capacitor at ref pin, f clk = 4.8mhz (50% duty cycle); t a = t min to t max unless otherwise noted. typical values are at t a = +25?.) conditions units min typ max symbol parameter 0 to 0.5ma output load to power down the internal reference for small adjustments t a = 0? to +70? on/off-leakage current, v in = 0 or v dd unipolar, v com = 0 v 1.0 v dd + 50mv v ref ref input voltage range ? 4.7 10 capacitive bypass at ref ? 0.01 1 capacitive bypass at refadj mv/ma 0.2 load regulation (note 7) v v dd - 1.0 refadj high threshold mv ?00 refadj input range ?0 ppm/? tc ref ref temperature coefficient ma 15 ref short-circuit current v 2.49 2.5 2.51 ref output voltage pf 12 c in input capacitance ? ?.01 1 multiplexer leakage current v analog input voltage rangesingle-ended and differential (note 6) 0v ref v in cs = v dd i source = 1ma i sink = 1.6ma v in = 0 or v dd v logic = 2.7v ? ?.1 ? i leakage three-state leakage current v v logic - 0.5 v oh output high voltage v 0.4 v ol output low voltage pf 15 c in input capacitance ? ?.1 ? i in input leakage current mv 200 v hys input hysteresis 2.0 cs = v dd pf 15 c out three-state output capacitance bipolar, v com = v ref / 2 -v ref /2 +v ref /2 v ref = 2.5v, f sample = 250ksps ? 200 300 i ref ref input current shutdown mode 2 v logic = 1.8v v 1.5 v ih input high voltage v logic = 1.8v v 0.5 v il input low voltage v logic = 2.7v 0.8 analog inputs internal reference external reference at ref digital inputs and outputs downloaded from: http:///
max1291/max1293 250ksps, +3v, 8-/4-channel, 12-bit adcs with +2.5v reference and parallel interface 4 _______________________________________________________________________________________ timing characteristics(v dd = v logic = +2.7v to +3.6v, com = gnd, refadj = v dd , v ref = +2.5v, 4.7? capacitor at ref pin, f clk = 4.8mhz (50% duty cycle); t a = t min to t max , unless otherwise noted. typical values are at t a = +25?.) conditions units min typ max symbol parameter shutdown mode standby mode operating mode,f sample = 250ksps ? 21 0 0.9 1.2 ma 2.3 2.6 v 2.7 3.6 v dd analog supply voltage 150 electrical characteristics (continued)(v dd = v logic = +2.7v to +3.6v, com = gnd, refadj = v dd , v ref = +2.5v, 4.7? capacitor at ref pin, f clk = 4.8mhz (50% duty cycle); t a = t min to t max unless otherwise noted. typical values are at t a = +25?.) v logic current i logic c l = 20pf 21 0 ? power-supply rejection psr v dd = 3v ?0%, full-scale input ?.4 ?.9 mv f sample = 250ksps not converting v 1.8 v dd + 0.3 v logic digital supply voltage wr to clk fall setup time t cws 40 ns ns clk pulse width high ns clk period t ch 40 t cp 208 clk pulse width low t cl 40 ns data valid to wr rise time t ds 40 ns wr rise to data valid hold time t dh 0 ns clk fall to wr hold time t cwh 40 ns cs to clk or wr setup time t csws 60 ns clk or wr to cs hold time t cswh 0 ns cs pulse width t cs 100 ns wr pulse width (note 8) t wr 60 ns t tc 20 100 ns c load = 20pf (figure 1) parameter symbol min typ max units conditions cs rise to output disable power requirements internal reference internal reference external reference external reference 1.9 2.3 0.5 0.8 i dd positive supply current downloaded from: http:///
max1291/max1293 250ksps, +3v, 8-/4-channel, 12-bit adcs with +2.5v reference and parallel interface _______________________________________________________________________________________ 5 note 1: tested at v dd = +3v, com = gnd, unipolar single-ended input mode. note 2: relative accuracy is the deviation of the analog value at any code from its theoretical value after offset and gain errors havebeen removed. note 3: offset nulled. note 4: on channel is grounded; sine wave applied to off channels. note 5: conversion time is defined as the number of clock cycles times the clock period; clock has 50% duty cycle. note 6: input voltage range referenced to negative input. the absolute range for the analog inputs is from gnd to v dd . note 7: external load should not change during conversion for specified accuracy. note 8: when bit 5 is set low for internal acquisition, wr must not return low until after the first falling clock edge of the conversion. timing characteristics (continued)(v dd = v logic = +2.7v to +3.6v, com = gnd, refadj = v dd , v ref = +2.5v, 4.7? capacitor at ref pin, f clk = 4.8mhz (50% duty cycle); t a = t min to t max , unless otherwise noted. typical values are at t a = +25?.) t tr 20 70 ns c load = 20pf, figure 1 rd rise to output disable rd fall to output data valid t do 20 70 ns rd fall to int high delay t int1 100 ns cs fall to output data valid t do2 110 ns c load = 20pf, figure 1 c load = 20pf, figure 1 c load = 20pf, figure 1 parameter symbol min typ max units conditions hben to output data valid t do1 20 110 ns c load = 20pf, figure 1 3k 3k dout dout v logic a) high-z to v oh and v ol to v oh b) high-z to v ol and v oh to v ol c load 20pf c load 20pf figure 1. load circuits for enable/disable times downloaded from: http:///
max1291/max1293 250ksps, +3v, 8-/4-channel, 12-bit adcs with +2.5v reference and parallel interface 6 _______________________________________________________________________________________ typical operating characteristics (v dd = v logic = +3v, v ref = +2.500v, f clk = 4.8mhz, c l = 20pf, t a = +25?, unless otherwise noted.) -0.5 -0.2-0.3 -0.4 -0.1 0 0.1 0.2 0.3 0.4 0.5 0 2000 1000 3000 4000 5000 integral nonlinearity vs. digital output code max1291/93 toc01 digital output code inl (lsb) -0.5 -0.2-0.3 -0.4 -0.1 0 0.1 0.2 0.3 0.4 0.5 0 2000 1000 3000 4000 5000 differential nonlinearity vs. digital output code max1291/93 toc02 digital output code dnl (lsb) 0.1 10k 10 1 100 1k 100k 1m supply current vs. sample frequency max1291/93 toc03 f sample (hz) i dd ( a) 1 10 100 1000 10,000 with internal reference with external reference 1.80 1.901.85 2.001.95 2.05 2.10 2.7 3.0 3.3 3.6 supply current vs. supply voltage max1291/93 toc04 v dd (v) i dd (ma) r l = code = 101010100000 1.6 1.81.7 2.01.9 2.1 2.2 -40 10 -15 35 60 85 supply current vs. temperature max1291/3 toc05 temperature (?) i dd (ma) r l = code = 101010100000 880 890 910900 920 930 standby current vs. supply voltage max1291/3 toc06 v dd (v) standby i dd ( a) 2.7 3.3 3.0 3.6 880 890 910900 920 930 standby current vs. temperature max1291/3 toc07 temperature (?) standby i dd ( a) -40 10 -15 35 85 60 0.50 1.000.75 1.25 1.50 2.7 3.0 3.3 3.6 power-down current vs. supply voltage max1291/3 toc08 v dd (v) power-down i dd ( a) 0.8 0.9 1.0 1.1 1.2 power-down current vs. temperature max1291/3 toc09 temperature (?) power-down i dd ( a) -40 35 -15 10 60 85 downloaded from: http:///
max1291/max1293 250ksps, +3v, 8-/4-channel, 12-bit adcs with +2.5v reference and parallel interface _______________________________________________________________________________________ 7 2.48 2.49 2.512.50 2.52 2.53 internal reference voltage vs. temperature max1291/3 toc11 temperature (?) v ref (v) -40 10 -15 35 60 85 -2.5 -2.0 -1.0-1.5 -0.5 0.0 offset error vs. supply voltage max1291/3 toc12 v dd (v) offset error (lsb) 2.7 3.3 3.0 3.6 -2.5 -1.5-2.0 -0.5-1.0 0.0 0.5 -40 10 -15 35 60 85 offset error vs. temperature max1291/3 toc13 temperature (?) offset error (lsb) -3 -1-2 0 1 2.7 3.3 3.0 3.6 gain error vs. supply voltage max1291/3 toc14 v dd (v) gain error (lsb) -2.0 -1.5 -0.5-1.0 0.0 0.5 gain error vs. temperature max1291/3 toc15 temperature (?) gain error (lsb) -40 10 -15 35 60 85 50 150100 200 250 2.7 3.3 3.0 3.6 logic supply current vs. supply voltage max1291/3 toc16 v dd (v) i logic ( a) 50 100 150 200 250 logic supply current vs. temperature max1291/3 toc17 temperature ( c) i logic ( a) -40 10 35 -15 60 85 typical operating characteristics (continued) (v dd = v logic = +3v, v ref = +2.500v, f clk = 4.8mhz, c l = 20pf, t a = +25?, unless otherwise noted.) 2.48 2.49 2.512.50 2.52 2.53 internal reference voltage vs. supply voltage max1291/3 toc10 v dd (v) v ref (v) 2.7 3.3 3.0 3.6 -140 -120 -100 -80 -60 -40 -20 0 20 0 400 200 600 800 1000 1200 fft plot max1291/93 toc18 frequency (khz) amplitude (db) v dd = 3v f in = 50khz f sample = 250ksps downloaded from: http:///
max1291/max1293 250ksps, +3v, 8-/4-channel, 12-bit adcs with +2.5v reference and parallel interface 8 _______________________________________________________________________________________ pin description name 1 hben high byte enable. used to multiplex the 12-bit conversion result. 1: four msbs are multiplexed on the data bus. 0: eight lsbs are available on the data bus. 2 d7 three-state digital i/o line (d7) 3 d6 three-state digital i/o line (d6) 4 d5 three-state digital i/o line (d5) 5 d4 three-state digital i/o line (d4) 6 d3/d11 three-state digital i/o line (d3, hben = 0; d11, hben = 1) 7 d2/d10 three-state digital i/o line (d2, hben = 0; d10, hben = 1) 8 d1/d9 three-state digital i/o line (d1, hben = 0; d9, hben = 1) 9 d0/d8 three-state digital i/o line (d0, hben = 0; d8, hben = 1) 10 int int goes low when the conversion is complete and the output data is ready. 11 rd active-low read select. if cs is low, a falling edge on rd enables the read operation on the data bus. 12 wr active-low write select. when cs is low in internal acquisition mode, a rising edge on wr latches in configuration data and starts an acquisition plus a conversion cycle. when cs is low in external acquisition mode, the first rising edge on wr ends acquisition and starts a conversion. 13 clk clock input. in external clock mode, drive clk with a ttl/cmos-compatible clock. ininternal clock mode, connect this pin to either v dd or gnd. 14 cs active-low chip select. when cs is high, digital outputs ( int , d7?0) are high imped- ance. 15 ch7 analog input channel 7 16 ch6 analog input channel 6 17 ch5 analog input channel 5 18 ch4 analog input channel 4 19 ch3 analog input channel 3 20 ch2 analog input channel 2 21 ch1 analog input channel 1 22 ch0 analog input channel 0 23 com ground reference for analog inputs. sets zero-code voltage in single-ended mode andmust be stable to ?.5 lsb during conversion. 24 gnd analog and digital ground 25 refadj bandgap reference output/bandgap reference buffer input. bypass to gnd with a0.01? capacitor. when using an external reference, connect refadj to v dd to disable the internal bandgap reference. 26 ref bandgap reference buffer output/external reference input. add a 4.7? capacitor tognd when using the internal reference. 27 v dd analog +5v power supply. bypass with a 0.1? capacitor to gnd. 28 v logic digital power supply. v logic powers the digital outputs of the data converter and can range from +1.8v to v dd + 300mv. 1 2 pin 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 function max1291 max1293 downloaded from: http:///
detailed description converter operation the max1291/max1293 adcs use a successive-approximation (sar) conversion technique and an input track/hold (t/h) stage to convert an analog input signal to a 12-bit digital output. their parallel (8 + 4) output format provides an easy interface to standard microprocessors (?s). figure 2 shows the simplified internal architecture of the max1291/max1293. single-ended and pseudo-differential operation the sampling architecture of the adc? analog com-parator is illustrated in the equivalent input circuit in figure 3. in single-ended mode, in+ is internally switched to channels ch0?h7 for the max1291 (figure 3a) and to ch0?h3 for the max1293 (figure 3b), while in- is switched to com (table 3). in differential mode, in+ and in- are selected from ana- log input pairs (table 4) and are internally switched to either of the analog inputs. this configuration is pseu- do-differential in that only the signal at in+ is sampled. the return side (in-) must remain stable within ?.5 lsb(?.1 lsb for best performance) with respect to gnd during a conversion. to accomplish this, connect a 0.1? capacitor from in- (the selected input) to gnd. during the acquisition interval, the channel selected as the positive input (in+) charges capacitor c hold . at the end of the acquisition interval, the t/h switchopens, retaining charge on c hold as a sample of the signal at in+.the conversion interval begins with the input multiplex- er switching c hold from the positive input (in+) to the negative input (in-). this unbalances node zero at thecomparator? positive input. the capacitive digital-to- analog converter (dac) adjusts during the remainder of the conversion cycle to restore node zero to 0v within the limits of 12-bit resolution. this action is equivalent to transferring a 12pf[(v in+ ) - (v in- )] charge from c hold to the binary-weighted capacitive dac, which in turnforms a digital representation of the analog input signal. max1291/max1293 250ksps, +3v, 8-/4-channel, 12-bit adcs with +2.5v reference and parallel interface _______________________________________________________________________________________ 9 t/h three-state, bidirectional i/o interface 12 17k 8 8 4 8 4 8 successive- approximation register mux charge redistribution 12-bit dac clock ( ) are for max1291 only. analog input multiplexer control logic & latches ref refadj 1.22v reference d0?7 8-bit data bus (ch5)(ch4) (ch7)(ch6) ch3ch2 ch1 ch0 com clk cs wr rd v dd hben gnd v logic max1291max1293 a v = 2.05 comp int figure 2. simplified internal architecture for 8-/4-channel max1291/max1293 downloaded from: http:///
max1291/max1293 analog input protection internal protection diodes, which clamp the analoginput to v dd and gnd, allow each input channel to swing within (gnd - 300mv) to (v dd + 300mv) without damage. however, for accurate conversions near fullscale, both inputs must not exceed (v dd + 50mv) or be less than (gnd - 50mv).if an off-channel analog input voltage exceeds the sup- plies by more than 50mv, limit the forward-bias input current to 4ma. track/hold the max1291/max1293 t/h stage enters its trackingmode on the rising edge of wr . in external acquisition mode, the part enters its hold mode on the next risingedge of wr . in internal acquisition mode, the part enters its hold mode on the fourth falling edge of clockafter writing the control byte. note that, in internal clock mode, this occurs approximately 1? after writing the control byte. in single-ended operation, in- is connect- ed to com and the converter samples the positive (?? input. in pseudo-differential operation, in- connects to the negative input (??, and the difference of ? (in+) - (in-) ? is sampled. at the beginning of the next conversion, thepositive input connects back to in+ and c hold charges to the input signal.the time required for the t/h stage to acquire an input signal depends on how quickly its input capacitance is charged. if the input signal? source impedance is high, the acquisition time lengthens, and more time must be allowed between conversions. the acquisition time, t acq , is the maximum time the device takes to acquire the signal and is also the minimum time required for thesignal to be acquired. calculate this with the following equation: t acq = 9 (r s + r in ) c in where r s is the source impedance of the input signal, r in (800 ) is the input resistance, and c in (12pf) is the adc? input capacitance. source impedances below 3k have no significant impact on the max1291/ max1293? ac performance.higher source impedances can be used if a 0.01? capacitor is connected to the individual analog inputs. together with the input impedance, this capacitor forms an rc filter, limiting the adc? signal bandwidth. input bandwidth the max1291/max1293 t/h stage offers a 250khz full-linear and a 3mhz full-power bandwidth, enabling these parts to use undersampling techniques to digitize high-speed transients and measure periodic signals with bandwidths exceeding the adc? sampling rate. to avoid high-frequency signals being aliased into the frequency band of interest, anti-alias filtering is recom- mended. starting a conversion initiate a conversion by writing a control byte thatselects the multiplexer channel and configures the max1291/max1293 for either unipolar or bipolar opera- tion. a write pulse ( wr + cs ) can either start an acqui- sition interval or initiate a combined acquisition plus 250ksps, +3v, 8-/4-channel, 12-bit adcs with +2.5v reference and parallel interface 10 ______________________________________________________________________________________ ch0 ch2 ch1 ch3 ch4ch6 ch7 ch5 com c switch track t/h switch r in 800 c hold hold 12-bit capacitive dac ref zero comparator + 12pf single-ended mode: in+ = ch0?h7, in- = com pseudo-differential mode: in+ and in- selected from pairs of ch0/ch1, ch2/ch3, ch4/ch5, and ch6/ch7 at the sampling instant,the mux input switches from the selected in+ channel to the selected in- channel. input mux figure 3a. max1291 simplified input structure ch0 ch1 ch2 ch3 com c switch track t/h switch r in 800 c hold hold 12-bit capacitive dac ref zero comparator + 12pf single-ended mode: in+ = ch0?h3, in- = com pseudo-differential mode: in+ and in- selected from pairs of ch0/ch1 and ch2/ch3 at the sampling instant,the mux input switches from the selected in+ channel to the selected in- channel. input mux figure 3b. max1293 simplified input structure downloaded from: http:///
conversion. the sampling interval occurs at the end ofthe acquisition interval. the acqmod (acquisition mode) bit in the input control byte (table 1) offers two options for acquiring the signal: an internal and an external acquisition. the conversion period lasts for 13 clock cycles in either the internal or external clock or acquisition mode. writing a new control byte during a conversion cycle aborts the conversion and starts a new acquisition interval. internal acquisition select internal acquisition by writing the control bytewith the acqmod bit cleared (acqmod = 0). this causes the write pulse to initiate an acquisition interval whose duration is internally timed. conversion starts when this acquisition interval ends (three external cycles or approximately 1? in internal clock mode) (figure 4). note that, when the internal acquisition is combined with the internal clock, the aperture jitter can be as high as 200ps. internal clock users wishing to achieve the 50ps jitter specification should always use external acquisition mode. external acquisition use external acquisition mode for precise control of thesampling aperture and/or dependent control of acquisi- tion and conversion times. the user controls acquisition and start-of-conversion with two separate write pulses. the first pulse, written with acqmod = 1, starts an acquisition interval of indeterminate length. the second write pulse, written with acqmod = 0, terminates acquisition and starts conversion on wr ? rising edge (figure 5).the address bits for the input multiplexer must have the same values on the first and second write pulse. power-down mode bits (pd0, pd1) can assume new values on the second write pulse (see the power-down modes section). changing other bits in the control byte corrupts the conversion. reading a conversion a standard interrupt signal int is provided to allow the max1291/max1293 to flag the microprocessor whenthe conversion has ended and a valid result is avail- able. int goes low when the conversion is complete and the output data is ready (figures 4 and 5). itreturns high on the first read cycle or if a new control byte is written. max1291/max1293 250ksps, +3v, 8-/4-channel, 12-bit adcs with +2.5v reference and parallel interface ______________________________________________________________________________________ 11 table 1. control byte functional description acqmod = 0: internal acquisition modeacqmod = 1: external acquisition mode acqmod d5 full power-down mode. clock mode is unaffected. pd1 and pd0 select the various clock and power-down modes. d7, d6 0 pd1, pd0 bit normal operation mode. internal clock mode selected. address bits a2, a1, a0 select which of the 8/4 (max1291/max1293) channels are to be converted (see tables 3, 4). a2, a1, a0 1 normal operation mode. external clock mode selected. d2, d1, d0 uni/ bip = 0: bipolar mode uni/ bip = 1: unipolar mode in unipolar mode, an analog input signal from 0 to v ref can be converted; in bipolar mode, the sig- nal can range from -v ref /2 to +v ref /2. 1 1 0 standby power-down mode. clock mode is unaffected. uni /bip d3 0 1 sgl /dif = 0: pseudo-differential analog input mode sgl /dif = 1: single-ended analog input mode in single-ended mode, input signals are referred to com. in pseudo-differential mode, the voltagedifference between two channels is measured (see tables 2, 3). sgl /dif 0 d4 function name downloaded from: http:///
max1291/max1293 250ksps, +3v, 8-/4-channel, 12-bit adcs with +2.5v reference and parallel interface 12 ______________________________________________________________________________________ t cs t csws t wr t conv t dh t acq t ds t int1 t d0 t d01 t tr high-z high-z high-z high-z cswr d7?0 int rdhben dout acqmod = "0" high/low byte valid high/low byte valid control byte t cswh figure 4. conversion timing using internal acquisition mode t cs t wr t acq t conv t dh t dh t ds t int1 t d0 t d01 t tr t cshw t csws acqmod = "1" cs wr d7?0 high-z high-z int rd hbendout acqmod = "0" high/low byte valid high/low byte valid control byte control byte high-z high-z figure 5. conversion timing using external acquisition mode downloaded from: http:///
max1291/max1293 250ksps, +3v, 8-/4-channel, 12-bit adcs with +2.5v reference and parallel interface ______________________________________________________________________________________ 13 selecting clock mode the max1291/max1293 operate with either an internalor an external clock. control bits d6 and d7 select either internal or external clock mode. the parts retain the last requested clock mode if a power-down mode is selected in the current input word. for both internal and external clock mode, internal or external acquisition can be used. at power-up, the max1291/max1293 enter the default external clock mode. internal clock mode select internal clock mode to release the ? from theburden of running the sar conversion clock. to select this mode, bit d7 of the control byte must be set to 1 and bit d6 must be set to 0. the internal clock frequen- cy is then selected, resulting in a conversion time of 3.6?. when using the internal clock mode, tie the clk pin either high or low to prevent the pin from floating. external clock mode to select the external clock mode, bits d6 and d7 ofthe control byte must be set to 1. figure 6 shows the clock and wr timing relationship for internal (figure 6a) and external (figure 6b) acquisition modes with anexternal clock. for proper operation, a 100khz to 4.8mhz clock frequency with 30% to 70% duty cycle is recommended. operating the max1291/max1293 with clock frequencies lower than 100khz is not recom- mended, because it causes a voltage droop across thehold capacitor in the t/h stage that results in degraded performance. digital interface input (control byte) and output data are multiplexed ona three-state parallel interface. this parallel interface (i/o) can easily be interfaced with standard ?s. the signals cs , wr, and rd control the write and read operations. cs represents the chip select signal, which enables a ? to address the max1291/max1293 as ani/o port. when high, cs disables the clk wr and rd inputs and forces the interface into a high-impedance(high-z) state. input format the control byte is latched into the device on pinsd7?0 during a write command. table 2 shows the control byte format. output format the output format for both the max1291/max1293 isbinary in unipolar mode and two? complement in bipo- lar mode. when reading the output data, cs and rd must be low. when hben = 0, the lower 8 bits areread. with hben = 1, the upper 4 bits are available and the output data bits d7?4 are set either low in unipolar mode or set to the value of the msb in bipolar mode (table 5). wr clkclk wr wr goes high when clk is high. wr goes high when clk is low. t cws t ch t cl t cp t cwh acquisition starts acquisition starts conversion starts conversion starts acquisition ends acquisition ends acqmod = "0" acqmod = "0" figure 6a. external clock and wr timing (internal acquisition mode) downloaded from: http:///
max1291/max1293 250ksps, +3v, 8-/4-channel, 12-bit adcs with +2.5v reference and parallel interface 14 ______________________________________________________________________________________ table 3. channel selection for single-ended operation (sgl/ dif = 1) * channels ch4?h7 apply to max1291 only. a1 ch0 0 + 0 0 a0 0 1 ch2 ch4* + 0 1 0 + ch3 - 0 ch1 ch7* - ch6* - com 1 ch5* 1 + - 0 0 0 a2 + 1 0 1 + 1 - - 1 0 1 1 1 + 1 - + - wr clkclk wr wr goes high when clk is high. wr goes high when clk is low. t dh t dh t cwh t cws acquisition starts acquisition starts conversion starts conversion starts acquisition ends acquisition ends acqmod = "1" acqmod = "1" acqmod = "0" acqmod = "0" figure 6b. external clock and wr timing (external acquisition mode) table 2. control byte format d7 (msb) d3 d1 d0 (lsb) d2 d5 pd1 uni/ bip a1 a0 a2 acqmod sgl/ dif pd0 d4 d6 downloaded from: http:///
max1291/max1293 250ksps, +3v, 8-/4-channel, 12-bit adcs with +2.5v reference and parallel interface ______________________________________________________________________________________ 15 table 4. channel selection for pseudo-differential operation (sgl/ dif = 0) * channels ch4?h7 apply to max1291 only. a1 ch0 0 + 0 - 0 a0 0 - 1 ch2 ch4* + 0 1 0 + - ch3 0 ch1 ch7* ch6* 1 ch5* 1 - + 0 0 0 a2 + - 1 0 1 - + 1 1 0 - 1 1 1 + 1 + - applications information power-on reset when power is first applied, internal power-on reset cir-cuitry activates the max1291/max1293 in external clock mode and sets int high. after the power supplies stabilize, the internal reset time is 10?, and no conver-sions should be attempted during this phase. when using the internal reference, 500? is required for v ref to stabilize. internal and external reference the max1291/max1293 can be used with an internalor external reference voltage. an external reference can be connected directly to ref or refadj. an internal buffer is designed to provide +2.5v at ref for the both the max1291 and the max1293. the internally trimmed +1.22v reference is buffered with a +2.05v/v gain. internal reference with the internal reference, the full-scale range is +2.5vwith unipolar inputs and ?.25v with bipolar inputs. the internal reference buffer allows for small adjustments (?00mv) in the reference voltage. see figure 7. note that the reference buffer must be compensated with an external capacitor (4.7? min) connected between ref and gnd to reduce reference noise and switching spikes from the adc. to further minimize noise on the reference, connect a 0.01? capacitor between refadj and gnd. external reference with both the max1291 and max1293, an external ref-erence can be placed at either the input (refadj) or the output (ref) of the internal reference buffer amplifier. using the refadj input makes buffering the external reference unnecessary. the refadj input impedance is typically 17k . table 5. data-bus output (8 + 4 parallelinterface) +3v 330k 50k gnd gnd 50k 0.01 f 4.7 f refadj ref max1291max1293 figure 7. reference voltage adjustment with externalpotentiometer d0 pin bit 0 (lsb) hben = 0 bit 8 hben = 1 bit 1 bit 9 d1 bit 2 bit 10 bit 3 bit 11 (msb) d3 d2 bit 5 bit 11 d5 bit 6 bit 11 bit 7 bit 11 d7 d6 bit 4 bit 11 d4 0 0 0 0 bipolar (uni/ bip = 0) unipolar (uni/ bip = 1) downloaded from: http:///
max1291/max1293 when applying an external reference to ref, disablethe internal reference buffer by connecting refadj to v dd . the dc input resistance at ref is 25k . therefore, an external reference at ref must deliver upto 200? dc load current during a conversion and have an output impedance less than 10 . if the refer- ence has higher output impedance or is noisy, bypassit close to the ref pin with a 4.7? capacitor. power-down modes save power by placing the converter in a low-currentshutdown state between conversions. select standby mode or shutdown mode using bits d6 and d7 of the control byte (tables 1 and 2). in both software power- down modes, the parallel interface remains active, but the adc does not convert. standby mode while in standby mode, the supply current is 850?(typ). the part powers up on the next rising edge on wr and is ready to perform conversions. this quick turn-on time allows the user to realize significantlyreduced power consumption for conversion rates below 250ksps. shutdown mode shutdown mode turns off all chip functions that draw qui-escent current, reducing the typical supply current to 2? immediately after the current conversion is complet- ed. a rising edge on wr causes the max1291/max1293 to exit shutdown mode and return to normal operation.to achieve full 12-bit accuracy with a 4.7? reference bypass capacitor, 500? is required after power-up. waiting 500? in standby mode, instead of in full-power mode, can reduce power consumption by a factor of 3 or more. when using an external reference, only 50? is required after power-up. enter standby mode by per- forming a dummy conversion with the control byte speci- fying standby mode. note: bypassing capacitors larger than 4.7? between ref and gnd results in longer power-up delays. transfer function table 6 shows the full-scale voltage ranges for unipolarand bipolar modes. figure 8 depicts the nominal, unipolar input/output (i/o) transfer function and figure 9 shows the bipolar i/o transfer function. code transitions occur halfway between successive-integer lsb values. output coding is binary, with 1 lsb = (v ref / 4096). maximum sampling rate/ achieving 300ksps when running at the maximum clock frequency of4.8mhz, the specified throughput of 250ksps is achieved by completing a conversion every 19 clock cycles: 1 write cycle, 3 acquisition cycles, 13 conver- 250ksps, +3v, 8-/4-channel, 12-bit adcs with +2.5v reference and parallel interface 16 ______________________________________________________________________________________ 111 . . . 111 111 . . . 110 100 . . . 010 100 . . . 001 100 . . . 000 011 . . . 111 011 . . . 110 011 . . . 101 000 . . . 001 000 . . . 000 1 02 input voltage (lsb) output code zs = com fs = ref + com fs 2048 (com) 1 lsb = ref 4096 fs - 3 / 2 lbs full-scaletransition figure 8. unipolar transfer function 011 . . . 111 011 . . . 110 000 . . . 010 000 . . . 001 000 . . . 000 111 . . . 111 111 . . . 110 111 . . . 101 100 . . . 001 100 . . . 000 - fs com* input voltage (lsb) output code zs = com +fs - 1 lsb *com v ref / 2 + com fs = ref 2 -fs = + com -ref 2 1 lsb = ref 4096 figure 9. bipolar transfer function downloaded from: http:///
max1291/max1293 250ksps, +3v, 8-/4-channel, 12-bit adcs with +2.5v reference and parallel interface ______________________________________________________________________________________ 17 table 6. full-scale and zero-scale for unipolar and bipolar operation unipolar mode bipolar mode com com zero scale zero scale -v ref /2 + com negative full scale v ref + com v ref /2 + com positive full scale full scale sion cycles, and 2 read cycles. this assumes that theresults of the last conversion are read before the next control byte is written. throughputs up to 300ksps can be achieved by first writing a control word to begin the acquisition cycle of the next conversion, and then read- ing the results of the previous conversion from the bus (figure 10). this technique allows a conversion to be completed every 16 clock cycles. note that the switch- ing of the data bus during acquisition or conversion can cause additional supply noise, which can make it difficult to achieve true 12-bit performance. layout, grounding, and bypassing for best performance use printed circuit (pc) boards.wire-wrap configurations are not recommended since the layout should ensure proper separation of analog and digital traces. do not run analog and digital lines parallel to each other, and don? lay out digital signal paths underneath the adc package. use separate analog and digital pc board ground sections with only one starpoint (figure 11) connecting the two ground systems (analog and digital). for lowest-noise opera- tion, ensure the ground return to the star ground? power supply is low impedance and as short as possi- ble. route digital signals far away from sensitive analog and reference inputs. high-frequency noise in the power supply (vdd) could influence the proper operation of the adc? fast com- parator. bypass v dd to the star ground with a network of two parallel capacitors, 0.1? and 4.7?, located asclose as possible to the max1291/max1293s?power supply pin. minimize capacitor lead length for best sup- ply-noise rejection; add an attenuation resistor (5 ) if the power supply is extremely noisy. definitions integral nonlinearity integral nonlinearity (inl) is the deviation of the valueson an actual transfer function from a straight line. this straight line can be either a best-straight-line fit or a line drawn between the endpoints of the transfer function, once offset and gain errors have been nullified. the static linearity parameters for the max1291/max1293 are measured using the endpoint method. differential nonlinearity differential nonlinearity (dnl) is the difference betweenan actual step width and the ideal value of 1 lsb. a dnl error specification of less than 1 lsb guarantees no missing codes and a monotonic transfer function. aperture definitions aperture jitter (t aj ) is the sample-to-sample variation in the time between the samples. aperture delay (t ad ) is the time between the rising edge of the sampling clockand the instant when an actual sample is taken. signal-to-noise ratio for a waveform perfectly reconstructed from digitalsamples, signal-to-noise ratio (snr) is the ratio of the full-scale analog input (rms value) to the rms quanti- zation error (residual error). the ideal, theoretical mini- mum analog-to-digital noise is caused by quantization error only and results directly from the adc? resolution (n bits): snr = (6.02 ? n + 1.76)db in reality, there are other noise sources besides quanti-zation noise: thermal noise, reference noise, clock jitter, etc. therefore, snr is computed by taking the ratio of the rms signal to the rms noise which includes all spectral components minus the fundamental, the first five harmonics, and the dc offset. signal-to-noise plus distortion signal-to-noise plus distortion (sinad) is the ratio of thefundamental input frequency? rms amplitude to the rms equivalent of all other adc output signals. sinad (db) = 20 ? log (signal rms / noise rms ) downloaded from: http:///
effective number of bits effective number of bits (enob) indicates the globalaccuracy of an adc at a specific input frequency and sampling rate. an ideal adc? error consists of quanti- zation noise only. with an input range equal to the full- scale range of the adc, calculate the effective number of bits as follows: enob = (sinad - 1.76) / 6.02 total harmonic distortion total harmonic distortion (thd) is the ratio of the rmssum of the first five harmonics of the input signal to the fundamental itself. this is expressed as: where v 1 is the fundamental amplitude, and v 2 through v 5 are the amplitudes of the 2nd- through 5th-order har- monics. spurious-free dynamic range spurious-free dynamic range (sfdr) is the ratio of therms amplitude of the fundamental (maximum signal component) to the rms value of the next largest distor- tion component. thd v v v v v log / = + + + ?? ?? ?? ? ?? ? 20 2 2 3 2 4 2 5 2 1 max1291/max1293 250ksps, +3v, 8-/4-channel, 12-bit adcs with +2.5v reference and parallel interface 18 ______________________________________________________________________________________ +3v v logic = +2v/+3v gnd supplies dgnd +2v/+3v com gnd 4.7 f 0.1 f v dd digital circuitry max1291max1293 r* = 5 *optional figure 11. power-supply and grounding connections clk acquisition control byte conversion low byte high byte d7?0 d11?8 low byte high byte d7?0 d11?8 acquisition sampling instant 123 4 5 6 78 91 01 11 21 31 41 51 6 wr rd hben d7?0 state control byte figure 10. timing diagram for fastest conversion chip information transistor count: 5781substrate connected to gnd downloaded from: http:///
max1291/max1293 250ksps, +3v, 8-/4-channel, 12-bit adcs with +2.5v reference and parallel interface ______________________________________________________________________________________ 19 typical operating circuits v dd ref refadj ch6ch5 ch4 ch3 ch2 ch1 ch0 com gnd 4.7 f 0.1 f +3v +1.8v to +3.6v +2.5v output status p control inputs clkcs wrrd d7 d6 d5 d4d3/d11 d2/d10 d1/d9 d0/d8 p data bus ch7 int hben p control inputs analog inputs v logic max1291 v dd ref refadj ch3ch2 ch1 ch0 com gnd 4.7 f 0.1 f +3v +1.8v to +3.6v +2.5v output status clkcs wrrd d7 d6 d5 d4d3/d11 d2/d10 d1/d9 d0/d8 p data bus int hben analog inputs v logic max1293 top view 2423 22 21 20 19 18 17 16 15 14 13 12 3 4 5 6 7 8 9 1011 12 v logic v dd refrefadj gnd com ch0 ch1 ch2 ch3 cs clk wr rd int d0/d8 d1/d9 d2/d10 d3/d11 d4 d5 d6 d7 hben qsop max1293 pin configurations (continued) part temp range pin-package inl (lsb) max1293 aceg 0? to +70? ?.5 24 qsop max1293beeg max1293aeeg -40? to +85? ? -40? to +85? ?.5 24 qsop 24 qsop ordering information (continued) max1293bceg 0? to +70? ? 24 qsop downloaded from: http:///
max1291/max1293 250ksps, +3v, 8-/4-channel, 12-bit adcs with +2.5v reference and parallel interface maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circuit patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 20 ____________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 2002 maxim integrated products printed usa is a registered trademark of maxim integrated products. qsop.eps package information (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline information, go to www.maxim-ic.com/packages .) downloaded from: http:///

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